Electrostatic discharge (ESD) is a problem in the utilization, manufacturing and/or design of the semiconductor devices. The integrated circuits manufactured on the semiconductor device can be damaged when ESD events are received from other circuits coupled to the semiconductor device or from people and/or machinery and tools touching the semiconductor device. During an ESD event, the integrated circuit may receive a charge which leads to relatively large voltages during a relatively short period of time. If, for example, the integrated circuit breaks down as the result of the high voltage and starts to conduct the charge of the ESD event, a current of several amperes may flow through the integrated circuit during a relatively short period of time. These currents may cause irreparable damage to the integrated circuit.
Today most integrated circuit comprise ESD protection circuitries that are able to conduct the charge of an ESD event to, for example, the ground without causing irreparable damage to the integrated circuit. Such ESD protection circuits are typically arranged near the I/O pads of the semiconductor device and are configured to conduct the charge of the ESD event directly to the ground before the current may reach the vulnerable portions of the integrated circuit.
Published U.S. Pat. No. 7,196,887B2 discloses an ESD protection device as presented in the cross-sectional view of FIG. 2 of that document, which is FIG. 1a of the current application. In the known prior art device a PMOS transistor is manufactured in a N-doped substrate 116. The N-doped substrate may also be an N-well in a P doped substrate. In the following the term N-well is used for this area. The drain and the source of the PMOS transistor are formed by the P+ regions 118, 120 which are isolated from each other by the gate oxide 140 (e.g. polysilicon) above which the gate 124 of the PMOS transistor is provided. As seen in the FIG. 1a, the P+ regions 118, 120 are silicided (regions 132) for allowing a good electrical contact to metal contacts of the contact layer which may be manufactured on top of the substrate. The silicided regions are not present below the gate oxide 140 and the polysilicon regions 126 extending in a lateral direction from the gate. As discussed in the cited patent, the structure also comprises a parasitic lateral PNP transistor 106 of which the collector is formed by the P+ area 118, the emitter is formed by the P+ area 120, and the base is formed by the N-well formed in the substrate 116. According to the cited patent, the N-well may be connected to the IO pad or to the bulk voltage which is assumed to be 0 volts or a lower voltage.
The operational characteristics of the ESD protection device of FIG. 1a are presented in FIG. 1b, which is a copy of FIG. 4 of the cited patent. The x-axis represents a voltage received by the I/O pad. The y-axis represents a current which flows through the ESD protection device (from I/O pad to ground). At a first triggering point 404 at trigger voltage Vt1, the current conducted through the ESD protection device increases while the voltage across the ESD protection device reduces towards the holding point 406, which the voltage is often termed the holding voltage Vh. The difference between the trigger voltage Vt1 to the holding voltage Vh is often termed the snapback voltage Vsp. From the holding point 406 the current through the ESD protection device increases towards a second triggering point 408 at which the ESD device breaks down. The operational region between the threshold point 404 and the second triggering point 408 is often termed the snapback region. The term snapback refers to the phenomena that from the first threshold point 404 the voltage across the ESD protection device initially decreases and from the holding point 406 slowly increases. Many ESD protection devices have operational characteristics which are similar to the characteristics presented in FIG. 1b and typically have a snapback operational region. It is to be noted that the characteristics presented in FIG. 1b relate, according to the cited patent application, to the structure presented in FIG. 1a. Most ESD protection device which have a snapback operational region, have a first triggering voltage Vt1 that is higher than the second triggering voltage Vt2.
In many applications, a strong snapback behaviour is not desired and, in other application, even no snapback behaviour is allowed. Thus, in these applications the snapback voltage Vsp should be as small as possible. Consequently, the ESD protection device of the cited patent application can not be used in such applications.